revision 2.1 jan. 2004 1 r0201-STC62WV1M8 very low power/voltage cmos sram 1m x 8 bit ? wide vcc operation voltage : 2.4v ~ 5.5v ? very low power consumption : vcc = 3.0v c-grade: 30ma (@55ns) operating current i -grade: 31ma (@55ns) operating current c-grade: 24ma (@70ns) operating current i -grade: 25ma (@70ns) operating current 1.5ua (typ.) cmos standby current vcc = 5.0v c-grade: 75ma (@55ns) operating current i -grade: 76ma (@55ns) operating current c-grade: 60ma (@70ns) operating current i -grade: 61ma (@70ns) operating current 8.0ua (typ.) cmos standby current ? high speed access time : -55 55ns -70 70ns ? automatic power down when chip is deselected t he stc 62wv1m8 is a high performance , ve ry low powe r cmos static random access memory organized as 1,048,576 words by 8 bits and operates from a wide range of 2.4v to 5.5v supply voltage. advanced cmos technology and circuit techniques provide both high speed and low power features with a typical cmos standby current of 1.5ua at 3v/25 o c and maximum access time of 55ns at 3.0v/85 o c. easy memory expansion is provided by an active low chip enable (ce1) , an active high chip enable (ce2) and active low output enable (oe) and three-state output drivers. t he STC62WV1M8 has an auto matic power down feature, reducing the power consumption significantly when chip is deselected. the STC62WV1M8 is available in 48b bga and 44l tsop2 packages. ? general description ? features ? functional block diagram ? product family ? pin configurations stc international limited . reserves the right to modi fy document con tents withou t notice. address input buffer row decoder memory array 2048 x 4096 column i/o write driver sense amp column decoder data buffer output address input buffer data buffer input control gnd vdd oe we ce2 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 a13 a17 a15 a18 a16 a14 a12 a7 a6 a5 a4 8 8 8 8 18 512 4096 2048 22 a11a9 a8 a3 a2 a1 a0a10 a19 STC62WV1M8 power dissipation speed ( ns ) standby ( i ccsb1 , max ) operating ( i cc , max ) product family operating temperature vcc range vcc=3v vcc=5v vcc=3v vcc=5v pkg type STC62WV1M8ec tsop2-44 STC62WV1M8fc +0 o c to +70 o c 2.4v ~ 5.5v 55 / 70 5ua 55ua 24ma 60ma bga-48-0912 STC62WV1M8ei tsop2-44 STC62WV1M8fi -40 o c to +85 o c 2.4v ~ 5.5v 55 / 70 10ua 110ua 25ma 61ma bga-48-0912 a4 a3 a2 a1 a0 ce1 nc nc dq0 dq1 vcc gnd dq2 dq3 nc nc we a19 a18 a17 a16 a15 a5 a6 a7 oe ce2 a8 nc nc dq7 dq6 gnd vcc dq5 dq4 nc nc a9 a10 a11 a12 a13 a14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 STC62WV1M8ec STC62WV1M8ei ce1 stc ? three state outputs and ttl compatible ? fully static operation ? data retention supply voltage as low as 1.5v ? easy expansion with ce1, ce2 and oe options 70ns 70ns 55ns : 3.0~5.5v 70ns : 2.7~5.5v g h f e d c b a 123456 a9 a8 a11 a10 a18 a19 a12 a14 a13 a15 we nc nc nc nc nc d3 d7 vss a17 a16 a7 vcc vss vcc d2 d1 d6 d5 vcc a5 oe a3 a0 a6 a4 a1 a2 ce2 nc nc nc nc nc ce1 d4 nc d0 48-ball bga top view .com .com .com
revision 2.1 jan. 2004 2 r0201-STC62WV1M8 name function a0-a19 address input these 20 address inputs select one of the 1,048,576 x 8-bit words in the ram ce1 chip enable 1 input ce2 chip enable 2 input ce1 is active low and ce2 is active high. both chip enables must be active when data read from or write to the device. if either chip enable is not active, the device is deselected and is in a standby power mode. the dq pins will be in the high impedance state when the device is deselected. we write enable input the write enable input is active low and controls read and write operations. with the chip selected, when we is high and oe is low, output data will be present on the dq pins; when we is low, the data present on the dq pins will be written into the selected memory location. oe output enable input the output enable input is active low. if the output enable is active while the chip is selected and the write enable is inactive, data will be present on the dq pins and they will be enabled. the dq pins will be in the high impedance state when oe is inactive. dq0-dq7 data input/output ports these 8 bi-directional ports are used to read data from or write data into the ram. vcc power supply gnd ground ? truth table ? pin descriptions stc c in input capacitance v in =0v 10 pf c dq input/output capacitance v i/o =0v 12 pf ? absolute maximum ratings (1) ? operating range ? capacitance (1) (ta = 25 o c, f = 1.0 mhz) 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 1. this parameter is guaranteed and not 100% tested. symbol parameter rating units v term terminal voltage with respect to gnd -0.5 to vcc+0.5 v t bias temperature under bias -40 to +85 o c t stg storage temperature -60 to +150 o c p t power dissipation 1.0 w i out dc output current 20 ma STC62WV1M8 range ambient temperature vcc commercial 0 o c to +70 o c2.4v ~ 5.5v industrial -40 o c to +85 o c2.4v ~ 5.5v mode we ce1 ce2 oe i/o operation vcc current xhxx not selected (power down) xxlx high z i ccsb , i ccsb1 output disabled h l h h high z i cc read h l h l d out i cc write l l h x d in i cc symbol parameter conditions max. unit .com .com .com .com
revision 2.1 jan. 2004 3 r0201-STC62WV1M8 1. typical characteristics are at ta = 25 o c. 2. fmax = 1/t rc . 3. these are absolute values with respect to device ground and all overshoots due to system or tester notice are included. 4. icc _max. is 31ma(@3.0v) / 76ma(@5.0v) under 55ns operation. 5.i ccs b1 is 5ua/55ua at vcc=3.0v/5.0v and t a =70 o c. ? data retention characteristics ( ta = -40 to + 85 o c ) 1. vcc = 1.5v, t a = + 25 o c 2. t rc = read cycle time 3. i cc dr (max.) is 1.3ua at t a =70 o c. ? dc electrical characteristics ( ta = -40 o c to + 85 o c ) stc ? low v cc data retention waveform (1) ( ce1 controlled ) ce1 data retention mode vcc t cdr vcc t r v ih v ih vcc v dr 1.5v R Q R Q R Q R Q R Q R Q R Q .com .com .com .com
revision 2.1 jan. 2004 4 jedec parameter name name description cycle time : 70ns unit t avax t rc read cycle time 70 -- -- 55 -- -- ns t avqv t aa address access time -- -- 70 -- -- 55 ns t e1lqv t acs1 chip select access time (ce1) -- -- 70 -- -- 55 ns t e2lqv t acs2 chip select access time (ce2) -- -- 70 -- -- 55 ns t glqv t oe output enable to output valid -- -- 35 -- -- 30 ns t elqx t clz chip select to output low z 10 -- -- 10 -- -- ns t glqx t olz output enable to output in low z 10 -- -- 10 -- -- ns t ehqz t chz chip deselect to output in high z -- -- 35 -- -- 30 ns t ghqz t ohz output disable to output in high z -- -- 30 -- -- 25 ns t axox t oh data hold from address change 10 -- -- 10 -- -- ns r0201-STC62WV1M8 ? ac electrical characteristics ( ta = -40 o c to + 85 o c ) read cycle ? ac test conditions (test load and input/output reference) ? key to switching waveforms waveform inputs outputs must be steady may change from h to l don t care: any change permitted does not apply must be steady will be change from h to l change : state unknown center line is high impedance ?off ?state may change from l to h will be change from l to h , stc STC62WV1M8 parameter input pulse levels vcc / 0v input rise and fall times 1v/ns input and output timing reference level 0.5vcc output load c l = 30pf+1ttl c l = 100pf+1ttl min. typ. max. vcc=2.7~5.5v min. typ. max. vcc=3.0~5.5v cycle time : 55ns .com .com .com .com
revision 2.1 jan. 2004 5 r0201-STC62WV1M8 ? switching waveforms (read cycle ) read cycle1 (1,2,4) t rc t oh t aa d out address t oh notes: 1. we is high in read cycle. 2. device is continuously selected when ce1 = v il and ce2 = v ih . 3. address valid prior to or coincident with ce1 transition low and ce2 transition high. 4. oe = v il . 5. the parameter is guaranteed but not 100% tested. stc STC62WV1M8 read cycle2 (1,3,4) t clz t chz (5) d out ce1 (5) t acs1 ce2 t acs2 read cycle3 (1,4) t oh t rc t oe d out ce1 oe address t clz (5) t acs1 t chz (1,5) t ohz (5) t olz t aa ce2 t acs2 .com .com .com .com
revision 2.1 jan. 2004 6 r0201-STC62WV1M8 ? ac electrical characteristics ( ta = -40 o c to + 85 o c ) write cycle ? switching waveforms (write cycle) write cycle1 (1) stc STC62WV1M8 jedec parameter name parameter name description cycle time : 70ns unit t avax t wc write cycle time 70 -- -- 55 -- -- ns t e1lwh t cw chip select to end of write 70 -- -- 55 -- -- ns t avw l t as address set up time 0 -- -- 0 -- -- ns t avwh t aw address valid to end of write 70 -- -- 55 -- -- ns t wlwh t wp write pulse width 35 -- -- 30 -- -- ns t whax t wr write recovery time (ce2,ce1 , we) 0 -- -- 0 -- -- ns t wloz t whz write to output in high z -- -- 30 -- -- 25 ns t dvwh t dw data to write time overlap 30 -- -- 25 -- -- ns t whdx t dh data hold from write time 0 -- -- 0 -- -- ns t ghoz t ohz output disable to output in high z -- -- 30 -- -- 25 ns t whqx t ow end of write to output active 5 -- -- 5 -- -- ns t wr t wc (3) t cw (11) (2) t wp t aw t ohz (4,10) t as (3) t dh t dw d in d out we ce1 oe address (5) ce2 (5) min. typ. max. min. typ. max. (vcc=2.7~5.5v) (vcc=3.0~5.5v) cycle time : 55ns .com .com .com .com
revision 2.1 jan. 2004 7 r0201-STC62WV1M8 write cycle2 (1,6) stc STC62WV1M8 notes: 1. we must be high during address transitions. 2. the internal write time of the memory is defined by the overlap of ce2, ce1 and we low. all signals must be active to initiate a write and any one signal can terminate a write by going inactive. the data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t wr is measured from the earlier of ce2 going low, or ce1 or we going high at the end of write cycle. 4. during this period, dq pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. if the ce2 high transition or ce1 low transition occurs simultaneously with the we low transitions or after the we transition, output remain in a high impedance state. 6. oe is continuously low (oe = v il ). 7. d out is the same phase of write data of this write cycle. 8. d out is the read data of next address. 9. if ce2 is high or ce1 is low during this period, dq pins are in the output state. then the data input signals of opposite phase to the outputs must not be applied to them. 10. the parameter is guaranteed but not 100% tested. 11. t cw is measured from the later of ce2 going high or ce1 going low to the end of write. t wc t cw (11) (2) t wp t aw t whz (4,10) t as t wr (3) t dh t dw d in d out we ce1 address t ow (7) (8) (8,9) ce2 (5) .com .com .com .com
revision 2.1 jan. 2004 8 ? ordering information stc ? package dimensions STC62WV1M8 r0201-STC62WV1M8 tsop2-44 note: stc (stc international limited.) assumes no responsibili ty for t he application or use o f a ny product or circuit described herei n. stc does n ot a uthorize its products for use as cr itical components in any application in which the failu re of the stc product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. STC62WV1M8 x x y y grade c: +0 o c ~ +70 o c i: -40 o c ~ +85 o c speed 55: 55ns 70: 70ns pkg material -: normal g: green p: pb free package e: tsop2-44 f: bga-48-0912 .com .com .com .com
revision 2.1 jan. 2004 9 STC62WV1M8 stc r0201-STC62WV1M8 e0.1 3: symbol "n" is the number of solder balls. 1: controlling dimensions are in millimeters. 2: pin#1 dot marking by laser or pad print. n e d notes: 48 12.0 9.0 e1 d1 e 3.75 5.25 0.75 side view d0.1 d1 1.4 max. e e1 0.25 d 0.05 solder ball 0.35 d 0.05 view a 3.375 2.625 ? package dimensions (continued) 48 mini-bga (9mm x 12mm) d .com .com .com
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